The invention relates generally to automatic test equipment for testing semiconductor devices, and more particularly a failure capture apparatus and method for use in a semiconductor device tester.
Semiconductor memory manufacturers continuously seek to minimize the costs of producing memory devices in order to remain competitive. One of the more important fabrication processes involves testing each device to ensure reliability and operability under various conditions. The equipment utilized to carry out the testing is often referred to as automatic test equipment, or xe2x80x9ctestersxe2x80x9d.
Conventional testers generally include circuitry that couples to one or more memories-under-test (MUT) and writes signals to selected locations in the MUT. The written signals are subsequently read back and captured by the tester for comparison with expected signals. The failure results of the comparison generally dictate whether the MUT passed the test or requires repair.
Many memory devices employ redundant rows and columns for use in repairing the device should fails be detected during testing. This feature substantially improves the yields in the numbers of commercially acceptable devices. Conventional memory testers typically include one or more redundancy repair stations to physically replace one or more rows or columns with available redundant rows/columns. Before the redundancy analysis can take place, however, the reliable initial capture of the failure data by the tester must occur.
Traditionally, testers have initially stored failure data in RAM memories having capacities similar in size to the MUT. Commonly referred to as catchrams, the memories typically store fail information at addresses that physically correspond to the address locations within the MUT. This approach conveniently provides a bit-image representation of the MUT, allowing a user to quickly identify clusters of fails that might relate to a particular fabrication problem. This is particularly important in an engineering development environment to diagnose processing problems in fabricating MUTs early on. Quick identification of processing problems in a production line is also important to minimize any downtime on the line and maximize product throughput and corresponding lot yields.
One construction of a catchram utilizes a 1-bit wide SRAM having a capacity substantially equivalent to that of a MUT. Known for it""s relatively high speed of operation in random mode, the SRAM provides a desirable memory type from the standpoint of operation. Unfortunately, SRAM production has dropped in recent years, with future availability doubtful. Consequently, the cost of an SRAM device is fairly high.
In an effort to create an SRAM-less catchram, those skilled in the art have utilized various DRAM implementations. DRAMs are relatively inexpensive and generally provide large capacity memories suitable for bit-image catchram applications. The devices include selectable modes of operation according to either a random mode (interleave) or burst mode (sequential). Unfortunately, in the random mode, DRAMs operate at substantially slower speeds than SRAM devices, requiring special techniques in order to operate successfully in catchram applications.
One proposal for using DRAMS in a failure capture memory, disclosed in U.S. Pat. No. 5,790,559 to Sato, employs banks of interleaved DRAMs to achieve acceptable speeds of operation during the DRAM random (interleaving) mode. The banks each have a storage capacity equivalent to that of the MUT and produce outputs that are interleaved to generate a faster serial bitstream. As an alternative to the random mode of operation, the patent also discloses a technique that uses the burst mode in combination with an address converter to simultaneously store multiple bits of fail data sequentially in the capture memory.
While the Sato proposals appear beneficial for their intended applications, they employ several banks of DRAM devices for each MUT. For testers that process as many as 16 to 32 MUTs in parallel, the number of DRAMs required for all the catchrams approaches undesirable levels, both in terms of space and hardware cost. Additionally, with MUT capacities ever increasing in size, the corresponding conventional catchram capacities also increase, presenting cost concerns regarding the larger memories.
A technique proposed by Ohsawa in U.S. Pat. No. 5,644,578, allegedly addresses the memory capacity problem above by compressing failure data and storing the compressed failure data in a capture memory having a capacity less than that of a MUT. While this proposal allegedly reduces the size and cost of the capture memory, the storage scheme still relies on a physical correspondence between the position of the failed MUT memory cells and the capture memory locations.
A further compression scheme, disclosed generally in both U.S. Pat. Nos. 5,317,573 and 4,628,509, avoids the use of a catchram entirely. The technique generally includes a compressed matrix construction to track specific xe2x80x9cmust-failxe2x80x9d information to identify which redundant rows or columns of the MUT are required in order to repair the device. The compression matrix provides a limited number of addressable rows and columns (corresponding to the number of redundant rows and columns) that physically correspond to the failure addresses in the MUT.
While this data compression technique appears beneficial for fast production processing, the ability to provide any kind of bit-image analysis is omitted. Consequently, should devices consistently fail during production testing, any fabrication processing problems would not be readily apparent, possibly extending the time required for troubleshooting and repair.
What is needed and heretofore unavailable is a catchram construction that provides the capability of reconstructing a bit image map of the failure data from one or more MUTs, and maximizes the transfer of such information to redundancy analysis circuitry with minimal cost. The catchram and method of the present invention satisfies these needs.
The failure capture circuit of the present invention reduces costs involved in capturing and analyzing failure data from a memory-under-test (MUT). This is accomplished by storing minimal information indicative of MUT memory cell failures. By minimizing the stored failure information initially captured, subsequent transfer time for transmitting the failure information to a redundancy analysis circuit is also substantially minimized, increasing test throughput.
To realize the foregoing advantages, the invention in one form comprises a failure capture circuit for identifying failure location information from a memory-under-test (MUT) having a predetermined storage capacity. The failure capture circuit includes failure detection circuitry adapted for coupling to the MUT and operative to apply test signals to the MUT and process output signals therefrom into failure location information. A look-up table couples to the failure detection circuitry for storing the failure location information.
In another form, the invention comprises a failure processing circuit for determining failure data from a MUT and analyzing the failure data to repair the MUT. The failure processing circuit includes a failure capture circuit including failure detection circuitry adapted for coupling to the MUT and operative to apply test signals to the MUT. The failure detection circuitry also processes output signals from the MUT into failure information indicative of failed memory cell locations. A look-up table couples to the failure detection circuitry for storing the location information. The failure processing circuit further includes redundancy analysis circuitry to establish an optimal procedure for repairing the MUT. Transfer circuitry couples the redundancy analysis circuitry to the failure capture circuit and operates independently of the failure detection circuitry.
In yet another form, the invention comprises a screening circuit for distinguishing sparse-failure information from must-failure information, and selectively passing the sparse-failure information representing fail data from a MUT to a failure memory. The screening circuit also directs the sparse-fail and must-fail information to a redundancy analyzer. The screening circuit includes a column flag memory for tracking memory cell columns that have a predetermined number of failures defining must-fail columns and a row flag memory for tracking memory cell rows that have a predetermined number of failures defining must-fail rows. A row fail counter cooperates with the row and column flag memories to set flags according to pre-programmed threshold criteria.
A further form of the invention comprises a memory for use in a failure capture circuit for storing a plurality of multi-bit signals captured from a MUT. The signals have a preselected data structure. The memory includes a multi-bit input interface for receiving the multi-bit signals during a burst mode of operation and an array of storage cells disposed in communication with the input interface for storing the multi-bit signals.
In yet another form, the invention comprises a method of acquiring failure information from a MUT for subsequent redundancy analysis. The method includes the steps of capturing the failure information; identifying the locations of the failures inside the MUT from the failure information; and storing the identified failure locations in a look-up table.
In another form, the invention comprises a method of screening failure information passed to a failure capture memory adapted for storing failure address information from a MUT. The capture memory is accessible by a redundancy analysis circuit. The method includes the steps of determining must-fail information; separating the must-fail information from sparse-fail information; passing the sparse-fail information to the capture memory; and directing the must-fail information and the sparse-fail information to the redundancy analysis circuit.
Other features and advantages of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.